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engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 1/29 engineering specification type 15.0 sxga+ color tft/lcd module model name: N150P3-L04 document control number: oem i-N150P3-L04-03 note: specification is subject to change without notice. consequently it is better to contact international display technology before proceeding with the design of your product incorporating this module. sales support international display technology www..net
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 2/29 i contents i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 4.1 luminance uniformity 5.0 signal interface 5.1 connectors 5.2 interface signal connector 5.3 interface signal description 5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver 5.4.2 lvds receiver internal circuit 5.4.3 recommended guidelines for motherboard pcb design and cable selection 5.5 signal for lamp connector 6.0 pixel format image 7.0 parameter guide line for cfl inverter 8.0 interface timings 8.1 timing characteristics 8.2 timing definition 8.2.1 vertical timing table 8.2.2 horizontal timing table 9.0 power consumption 10.0 power on/off sequence 11.0 mechanical characteristics 12.0 national test lab requirement
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 3/29 ii record of revision date document revision page summary may 23,2003 oem i-N150P3-L04 all first edition for customer june 27, 2003 oem i-N150P3-L04-02 29 to add conditions of acceptability september 11, 2003 oem i-N150P3-L04-03 7 25 29 to update cfl current max 9.0 power consumption note 12.0 national test lab requirement
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 4/29 1.0 handling precautions ? if any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of the lcd module. ? the lcd panel and the cfl are made of glass and may break or crack if dropped on a hard surface, so please handle them with care. ? cmos-ics are included in the lcd panel. they should be handled with care, to prevent electrostatic discharge. ? do not press the reflector sheet at the back of the lcd module to any directions. ? do not stick the adhesive tape on the reflector sheet at the back of the lcd module. ? please handle care when mount in the system cover. mechanical damage for lamp cable and for lamp connector may cause safety problems. ? small amount of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source (2.5, iec60950 or ul60950), or be applied exemption conditions of flammability requirements (4.7.3.4, iec60950 or ul60950) in an end product. ? the lcd module is designed so that the cfl in it is supplied by limited current circuit (2.4, iec60950 or ul60950). ? the fluorescent lamp in the liquid crystal display(lcd) contains mercury. do not put it in trash that is disposed of in landfills. dispose of it as required by local ordinances or regulations. ? never apply detergent or other liquid directly to the screen. ? wipe off water drop immediately. long contact with water may cause discoloration or spots. ? when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or abrasives. ? do not touch the front screen surface in your system, even bezel. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by international display technology for any infringements of patents or other right of the third partied which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of international display technology or others. ? the information contained herein may be changed without prior notice. it is therefore advisable to contact international display technology before proceeding with the design of equipment incorporating this product.
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 5/29 2.0 general description this specification applies to the type 15.0 color tft/lcd module 'N150P3-L04'. this module is designed for a display unit of notebook style personal computer. the screen format and electrical interface are intended to support the sxga+(1400(h) x 1050(v)) screen. support color is native 262k colors (rgb 6-bit data driver). all input signals are lvds (low voltage differential signaling) interface compatible. this module does not contain an inverter card for backlight. 2.1 characteristics the following items are characteristics summary on the table under 25 degree c c ondition: characteristics items specifications screen diagonal [mm] 380.625 pixels h x v 1400(x3) x 1050 active area [mm] 304.5(h) x 228.375(v) pixel pitch [mm] 0.2175(per one triad) x 0.2175 pixel arrangement r,g,b vertical stripe weight [grams] 575 typ., 600 max. physical size [mm] 317.3(w) x 242.0(h) x 6.2(d) typ./6.5(d) max. display mode normally black display surface treatment glare (hard coat only) support color native 262k colors (rgb 6-bit data driver) white luminance [cd/m 2 ] (center) 200 typ. (icfl=6.5ma) contrast ratio 400 : 1 typ. optical rise time + fall time [msec] 60 typ., 120 max. nominal input voltage vdd [volt] +3.3 typ. power consumption [watt](vdd) 2.5 typ., 2.7 max. (vdd=3.3[v]) lamp power consumption [watt] 4.1 typ., 4.5 max. (w/o inverter loss) typical power consumption [watt] (vdd line + vcfl line) 6.6 typ., 7.2 max. (w/o inverter loss). (vdd=3.3[v]) electrical interface 8 pairs lvds (even/odd r/g/b data(6bit), 3sync signals, clock) temperature range [degree c] operating storage (shipping) 0 to +50 -20 to +60 cfl cable length [mm] 105 typ
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 6/29 2.2 functional block diagram the following diagram shows the functional block of this type 15.0 color tft/lcd module. the first lvds port transmits even pixels while the second lvds port transmits odd pixels. veedid x-driver tft rray/cell 6bit color data for r/g/b dtclk(even/odd) dsptmg hsync vsync vdd lcd controller lcd card backlight unit 1400(r/g/b)x1050 gnd dc-dc converter ref circuit (even/odd) < 8 pairs lvds > even pixel odd pixel dual lvds receive r lcd-drive connector y-driver g/a lamp connector jst bhsr-02vs-1 (2pin) jae fi-xb30sl-hf10 (30pin) clkeedid dataeedid eedid chi p
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 7/29 3.0 absolute maximum ratings absolute maximum ratings of the module is as follows: item symbol min max unit conditions logic/lcd drive voltage vdd -0.3 +4.0 v input signal voltage vin -0.3 vdd+0.3 v cfl ignition voltage vs - +2,000 vrms (note 2) cfl current icfl - 7 mams cfl peak inrush current icflp - 20 ma operating temperature top 0 +50 deg.c (note 1) operating relative humidity hop 8 95 %rh (note 1) storage temperature tst -20 +60 deg.c (note 1) storage relative humidity hst 5 95 %rh (note 1) vibration 1.5 10-200 g hz shock 50 18 g ms rectangle wave note 1: maximum wet-bulb should be 39 degree c and no condensation. note 2: duration : 50msec max. ta=0 degree c
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 8/29 4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 degree c condition: item conditions specification typ. note viewing angle (degrees) horizontal (right) k> 10 (left) 85 85 - - k: contrast ratio vertical (upper) k> 10 (lower) 85 85 - - contrast ratio 400 - response time (ms) rising + falling 60 - color red x 0.569 - chromaticity red y 0.332 - (cie) green x 0.312 - green y 0.544 - blue x 0.149 - blue y 0.132 - white x 0.313 - white y 0.329 - white luminance (cd/m 2 ) 200 typ. -
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 9/29 5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. connector name / designation for signal connector manufacturer jae type / part number fi-xb30sl-hf10 mating receptacle manufacture jae mating receptacle/part number fi-x30m connector name / designation for lamp connector manufacturer jst type / part number bhsr-02vs-1 mating type / part number sm02b-bhss-1
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 10/29 5.2 interface signal connector pin # signal name pin # signal name 1 gnd 16 gnd 2 vdd 17 reclkin- 3 vdd 18 reclkin+ 4 v eedid (note 2,3) 19 gnd 5 reserved (note 1) 20 roin0- 6 clk eedid (note 2,4) 21 roin0+ 7 data eedid (note 2,4) 22 gnd 8 rein0- 23 roin1- 9 rein0+ 24 roin1+ 10 gnd 25 gnd 11 rein1- 26 roin2- 12 rein1+ 27 roin2+ 13 gnd 28 gnd 14 rein2- 29 roclkin- 15 rein2+ 30 roclkin+ note: 1. 'reserved' pins are not allowed to connect any other line. 2. this lcd module complies with "vesa enhanced extended display identification data standard release a, revision 1" and supports "eedid version 1.3". this module uses serial eeprom at24c02-10ti-2.7 (atmel) or compatible as a eedid function. 3. v eedid power source shall be the current limited circuit which has not exceeding 1a. (reference document : "enhanced display data channel (e-ddc tm ) proposed standard", vesa) 4. both clk eedid line and data eedid line are pulled-up with 10k ohm resistor to v eedid power source line at lcd panel, respectively. voltage levels of all input signals are lvds compatible (except vdd,eedid). refer to "signal electrical characteristics for lvds", for voltage levels of all input signals.
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 11/29 5.3 interface signal description pin # signal name description 1 gnd ground 2 vdd +3.3v power supply 3 vdd +3.3v power supply 4 v eedid eedid 3.3v power supply 5 reserved reserved 6 clk eedid eedid clock 7 data eedid eedid data 8 rein0- negative lvds differential data input (even r0-r5, g0) 9 rein0+ positive lvds differential data input (even r0-r5, g0) 10 gnd ground 11 rein1- negative lvds differential data input (even g1-g5, b0-b1) 12 rein1+ positive lvds differential data input (even g1-g5, b0-b1) 13 gnd ground 14 rein2- negative lvds differential data input (even b2-b5, hsync, vsync, dsptmg) 15 rein2+ positive lvds differential data input (even b2-b5, hsync, vsync, dsptmg) 16 gnd ground 17 reclkin- negative lvds differential clock input (even) 18 reclkin+ positive lvds differential clock input (even) 19 gnd ground 20 roin0- negative lvds differential data input (odd r0-r5, g0) 21 roin0+ positive lvds differential data input (odd r0-r5, g0) 22 gnd ground 23 roin1- negative lvds differential data input (odd g1-g5, b0-b1) 24 roin1+ positive lvds differential data input (odd g1-g5, b0-b1) 25 gnd ground 26 roin2- negative lvds differential data input (odd b2-b5) 27 roin2+ positive lvds differential data input (odd b2-b5) 28 gnd ground 29 roclkin- negative lvds differential clock input (odd) 30 roclkin+ positive lvds differential clock input (odd) note: 1. input signals of odd and even clock shall be the same timing. 2. the module uses a 100ohm resistor between positive and negative data lines of each receiver input. 3. even: first pixel , odd: second pixel
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 12/29 signal name description +red 5 (er5/or5) red data 5 (msb) +red 4 (er4/or4) red data 4 +red 3 (er3/or3) red data 3 +red 2 (er2/or2) red data 2 +red 1 (er1/or1) red data 1 +red 0 (er0/or0) red data 0 (lsb) (even/odd) red-pixel data: each red pixel's brightness data consists of these 6 bits pixel data. +green 5 (eg5/og5) green data 5 (msb) +green 4 (eg4/og4) green data 4 +green 3 (eg3/og3) green data 3 +green 2 (eg2/og2) green data 2 +green 1 (eg1/og1) green data 1 +green 0 (eg0/og0) green data 0 (lsb) (even/odd) green-pixel data: each green pixel's brightness data consists of these 6 bits pixel +blue 5 (eb5/ob5) blue data 5 (msb) +blue 4 (eb4/ob4) blue data 4 +blue 3 (eb3/ob3) blue data 3 +blue 2 (eb2/ob2) blue data 2 +blue 1 (eb1/ob1) blue data 1 +blue 0 (eb0/ob0) blue data 0 (lsb) (even/odd) blue-pixel data: each blue pixel's brightness data consists of these 6 bits pixel data. dtclk data clock: the typical frequency is 54mhz/36mhz. (even/odd) the signal is used to strobe the pixel + data and the + dsptmg +dsptmg (dsp) when the signal is high, the pixel data shall be valid to be displayed. vsync (v-s) vertical sync: this signal is synchronized with dtclk. hsync (h-s) horizontal sync: this signal is synchronized with dtclk. vdd power supply gnd ground v eedid eedid 3.3v power supply clk edid eedid clock data eedid eedid data note: output signals except v eedid ,clk eedid and data eedid from any system shall be hi-z state when vdd is off. vsync should start with active high ( positive pulse ) signal from when vdd is supplied and its polarity should not be changed.
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 13/29 5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver the lvds receiver equipped in this lcd module is compatible with ansi/tia/tia-644 standard. table electrical characteristics parameter symbol min max unit conditions differential input high threshold vth +100 mv vcm=+1.2v differential input low threshold vtl -100 mv vcm=+1.2v magnitude differential input voltage |vid| 100 600 mv common mode voltage vcm 0.825 +|vid|/2 2.4 -|vid|/2 v vth - vtl = 200mv common mode voltage offset ? vcm -50 +50 mv vth - vtl = 200mv note: ? input signals shall be low or hi-z state when vdd is off. ? all electrical characteristics for lvds signal are defined and shall be measured at the interface connector of lcd. (see figure "measurement system" ). figure voltage definitions
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 14/29 figure measurement system table. switching characteristics parameter symbol min typ max unit conditions clock frequency fc 51 54 57 mhz cycle time tc 17.5 18.5 19.6 ns data setup time (note 2) tsu 700 ps data hold time (note 2) thd 700 ps fc = 54mhz, tccj < 50ps, vth-vtl = 200mv, vcm = 1.2v, ? vcm = 0 cycle-to-cycle jitter (note 3) tccj -150 +150 ps cycle modulation rate (note 4) tcjavg 20 ps/clk clock skew between lvds odd/even channels 1 ns note 1: all values are at vdd=3.3v, ta=25 degree c. note 2: see figure "timing definition" and "timing definition (detail a)" for definition. note 3: jitter is the magnitude of the change in input clock period. note 4: this specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. this specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps.
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 15/29 figure. timing definition (even)
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 16/29 figure. timing definition (odd)
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 17/29 figure. timing definition (detail a) note: tsu and thd are internal data sampling window of receiver. trskm is the system skew margin; i.e., the sum of cable skew, source clock jitter, and other inter-symbol interference, shall be less than trskm.
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 18/29 5.4.2 lvds receiver internal circuit below figure shows the internal block diagram of the lvds receiver. 5.4.3 recommended guidelines for motherboard pcb design and cable selection following the suggestions below will help to achieve optimal results. ? use controlled impedance media for lvds signals. they should have a matched differential impedance of 100ohm. ? match electrical lengths between traces to minimize signal skew. ? lsolate ttl signals from lvds signals. ? for cables, twisted pair, twinax, or flex circuit with close coupled differential traces are recommended.
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 19/29 5.5 signal for lamp connector pin # signal name 1 lamp high voltage 2 lamp low voltage
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 20/29 6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format image. even and odd pair of rgb data are sampled at a time. r g b r g b r g b r g b r g b r g b r g b r g b even odd even odd 0 1 1399 1st line 1050th line 1398
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 21/29 7.0 parameter guide line for cfl inverter parameter min dp-1 max units condition white luminance - 200 - cd/m 2 (ta=25 deg.c) cfl current (icfl) 3.0 6.5 7.0 marms (ta=25 deg.c) cfl frequency (fcfl) 40 70 khz (ta=25 deg.c) (note 1) cfl ignition voltage (vs) 1,600 - - vrms (ta=0 deg.c) (note 3) cfl voltage (reference)(vcfl) - 630 - vrms (ta=25 deg.c) (note 2) cfl power consumption (pcfl) - 4.1 4.5 w (ta=25 deg.c) (note 2) *1 all of characteristics listed are measured under the condition using the test inverter. *2 in case of using an inverter other than listed, it is recommended to check the inverter carefully. sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 in designing an inverter, it is suggested to check safety circuit very carefully. impedance of cfl, for instance, becomes more than 1 [m ohm] when cfl is damaged. *4 generally, cfl has some amount of delay time after applying kick-off voltage. it is recommended to keep on applying kick-off voltage for 1 [sec] until discharge. *5 reducing cfl current increases cfl discharge voltage and generally increases cfl discharge frequency. so all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. *6 it should be employed the inverter which has 'duty dimming', if icfl is less than 4[ma]. note 1: cfl discharge frequency should be carefully determined to avoid interference between inverter and tft lcd. note 2: calculated value for reference (icfl x vcfl = pcfl). note 3: cfl inverter should be able to give out a power that has a generating capacity of over 1,600 voltage. lamp units need 1,600 voltage minimum for ignition. note 4: dp-1 (design point-1) is recommended design point.
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 22/29 the following chart is luminance versus lamp power for your reference. tbd
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 23/29 8.0 interface timings basically, interface timings described here is not actual input timing of lcd module but output timing of sn75lvds86 (texas instruments) or equivalent. 8.1 timing characteristics timing characteristics signal item symbol min. typ. max. unit dtclk freqency fdck 51 54 57 [mhz] tck 18.5 [ns] frame rate fv - 60 - [hz] +v-sync tv - 16.67 - [ms] nv 1058 1066 2046 [lines] v-active level tva 15.63 46.89 969.06 [us] nva 1 3 62 [lines] v-back porch nvb 6 12 125 [lines] v-front porch nvf 1 1 [lines] +dsptmg v-line m 1050 [lines] scan rate fh - 63.98 - [khz] +h-sync th - 15.63 - [us] nh 762 844 1023 [tck] h-active level tha 1.037 [us] tha 8 56 250 [tck] h-back porch thb 26 64 300 [tck] h-front porch thf 8 24 [tck] +dsptmg display thd 12.96 [us] +data data even/odd n 1400 [dots] note: positive hsync polarity is recommended. only positive vsync is acceptable. when there are invalid timing, display appears black pattern. synchronous signal defects and enter auto refresh for lcd module protection mode.
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 24/29 8.2 timing definition 8.2.1 vertical timing table support mode tvblk vertical blanking m active field tvf vsync front porch tv,nv frame time tva vsync width tvb vsync back porch 1400 x 1050 (h line rate : 15.63 us) 0.250 ms (16 lines) 16.411 ms (1050 lines) 0.016 ms (1 line) 16.661 ms (1066 lines) 0.047 ms (3 lines) 0.188 ms (12 lines) tvblk m tvf tva tvb tv dsptmg +vsync 8.2.2 horizontal timing table support mode thblk horizontal blanking thd active field thf hsync front porch th,nh h line time tha hsync width thb hsync back porch 1400 x 1050 dotclock : 108.000 mhz (54.000mhz x2) 2.667 us (288 dots) 12.963 us (1400 dots) 0.444 us (48 dots) 15.630 us (1688 dots) 1.037 us (112 dots) 1.185 us (128 dots) thblk thd thf tha thb th dsptmg -hsync +hsync 02 4 n-4 n-2 video(even) video(odd) video(even) video(odd) dtclk 13 5 n-3 n-1 tck
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 25/29 9.0 power consumption input power specifications are as follows; symbol parameter min typ max units condition vdd logic/lcd drive voltage 3.0 3.3 3.6 [v] load capacitance 50 uf pdd vdd power 2.8 [w] max. pattern, vdd=3.6[v] pdd vdd power 2.5 2.7 [w] all white pattern, vdd=3.3[v] idd vdd current 930 [ma] max pattern, vdd=3.0[v] idd vdd current 760 [ma] all white pattern, vdd=3.3[v] vddrp allowable logic/lcd drive ripple voltage 100 [mvp-p] vddns allowable logic/lcd drive ripple noise 100 [mvp-p] note: max. pattern : horizontal pixel stripe.
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 26/29 10.0 power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. 90% 10% 10% 10% 90% 10ms max. 0 min. 0 v 0 v vdd signals 180ms min. 0 min. 10% 10% 150ms min. 100ms min. 20ms min. lamp 90% 90% on (recommended).
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 27/29 11.0 mechanical characteristics
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 28/29
engineering specification (c) copyright international display technology 2003 all rights reserved september 11,2003 oem i-N150P3-L04-03 29/29 12.0 national test lab requirement the display module will satisfy all requirements for compliance to ul 60950, 3rd edition u.s.a. information technology equipment can/csa-c22.2 no. 60950-00 canada, information technology equipment iec 60950 (3rd. ed.) international, information technology equipment en 60950 (3rd. ed.) international, information technology equipment (european norm for iec60950) conditions of acceptability for use only in or with complete equipment where the acceptability of the combination is determined by underwriters laboratories inc. when installed in an end-product, consideration must be given to the following: ? the terminals and connectors are suitable for factory wiring only. ? the component has been evaluated for use in a pollution degree 2 environment. ? need for fire and/or electrical enclosures hall be considered in end puroduct. ? the unit is intended to be supplied by selv and limited power source. also separated from electrical parts, which may produce high temperature that could cause ignition by at least 13 mm of air or by a solid barrier of material of v-1 minimum due to materials having no flammability rating. ? back light lamp is rated 630 v rms, 6.5 ma, and intended to be supplied by limited current circuit. ? insulation between backlight circuit and other selv circuit has not been evaluated. additional consideration shall be made if backlight is supplied by a source other than limited current circuit. ****** end of page ******

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